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SK Hynix believes in 600-layer 3D NAND flash



It’s not just Intel’s CEO who spoke about the company’s plans this week. Almost simultaneously with the keynote speech at the IEEE International Symposium, SK Hynix CEO Seok-Hee Lee made a speech. He shared his vision of the future in relation to the products manufactured by SK Hynix, that is, to memory chips.

The head of SK Hynix presented several conceptual developments that the company is working on right now. They refer to 3D NAND and DRAM memory.

If earlier the company believed that the scaling potential of 3D NAND is limited to about 500 layers, then recent studies allow the manufacturer to hope to master the production of 600-layer 3D NAND memory. Let us clarify that this is a matter for the distant future. So far, the company has managed to manufacture and test 176-layer 3D NAND chips with a density of 512 Gbps. A further increase in the number of layers requires the solution of several technical problems, including the improvement of dielectric materials and an increase in the uniformity of the formed layers.

A similar situation is observed in the development of DRAM. The manufacturer associates a further increase in density with the transition to EUV lithography, which will overcome the limitations of modern technology. At the same time, SK Hynix is ​​trying to reduce the thickness of the dielectric layer, develop new insulating materials with high dielectric constant and conductors with reduced resistance.

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