PLDA, a high-speed interconnect IP core, has unveiled an XpressRICH PCI Express controller IP core that meets PCIe 6.0 specifications. As you know, in PCIe 6.0, the data transfer rate reaches 64 GT / s, twice the capabilities of PCIe 5.0. The new version of the standard, expected to be adopted this year, will consolidate the transition to four-level pulse amplitude modulation (PAM4) and low-latency Forward Error Correction (FEC) and additional mechanisms to improve bandwidth efficiency.
The PCIe 6.0 architecture will go a long way for SoC designers and system architects building next-generation ICs that move large amounts of data across systems. Examples include supercomputers, cloud servers, AI and machine learning systems, enterprise storage and networking, and automotive solutions.
The presented IP core is flexible, meaning it can be fully parameterized using the included configuration assistant. It allows you to select data path configuration, buffer sizes and performance, number of lines (x1, x2, x4, x8 and x16), role (endpoint, root port, switch port, block, controller operating in dual mode), enable virtualization tools and data protection and configure other parameters.
PLDA expects to make the XpressRICH PCIe 6.0 IP core publicly available in the fourth quarter.
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